Design Summary: "run_benchmark"

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Full run_benchmark Metrics

- units import_verilog0 syn0 floorplan0 place0 cts0 route0 write_gds0 write_data0
errors 0 0 0 0 0 0 0 0
warnings 14 119 41 42 40 40 0 40
drvs --- --- --- 5 5 19 --- 19
drcs --- --- --- --- --- 0 --- ---
unconstrained --- --- 592 592 592 592 --- 592
cellarea um^2 --- 578.199 571.084 601.483 601.483 601.483 --- 601.483
totalarea um^2 --- --- 1434.960 1434.960 1434.960 1434.960 --- 1434.960
utilization % --- --- 39.798 41.916 41.916 41.916 --- 41.916
logicdepth --- --- 0 0 0 0 --- 0
peakpower mw --- --- 0.000 0.000 0.000 0.000 --- 0.000
leakagepower mw --- --- 0.000 0.000 0.000 0.000 --- 0.000
irdrop mv --- --- --- --- --- --- --- 0.003
holdpaths --- --- --- 0 0 0 --- 0
setuppaths --- --- --- 0 0 0 --- 0
macros --- --- 0 0 0 0 --- 0
cells --- 4881 4994 5049 5049 5049 --- 5049
registers --- 465 465 465 465 465 --- 465
buffers --- --- 33 88 88 88 --- 88
inverters --- --- 1003 1003 1003 1003 --- 1003
pins --- 354 354 354 354 354 --- 354
nets --- 6101 5620 5675 5675 5675 --- 5675
vias --- --- --- --- --- 36229 --- ---
wirelength um --- --- --- --- --- 10877.000 --- ---
memory B 259.629M 161.113M 518.355M 1.988G 575.879M 5.280G 583.008M 700.340M
exetime s 07.620 09.300 09.509 34.689 13.269 43.549 04.610 53.509
tasktime s 08.484 13.457 11.028 35.244 14.065 44.266 06.846 54.704
totaltime s 08.484 21.942 32.970 01:08.215 01:22.280 02:06.546 02:13.926 03:01.785
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Metrics for run_benchmark Tasks

Toggle import_verilog0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 14 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 259.629MB 07.620s 08.484s 08.484s
Toggle syn0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 119 --- --- --- 578.199um^2 --- --- --- --- --- --- --- --- --- 4881 465 --- --- 354 6101 --- --- 161.113MB 09.300s 13.457s 21.942s
Toggle floorplan0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 41 --- --- 592 571.084um^2 1434.960um^2 39.798% 0 0.000mw 0.000mw --- --- --- 0 4994 465 33 1003 354 5620 --- --- 518.355MB 09.509s 11.028s 32.970s
Toggle place0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 42 5 --- 592 601.483um^2 1434.960um^2 41.916% 0 0.000mw 0.000mw --- 0 0 0 5049 465 88 1003 354 5675 --- --- 1.988GB 34.689s 35.244s 01:08.215s
Toggle cts0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 40 5 --- 592 601.483um^2 1434.960um^2 41.916% 0 0.000mw 0.000mw --- 0 0 0 5049 465 88 1003 354 5675 --- --- 575.879MB 13.269s 14.065s 01:22.280s
Toggle route0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 40 19 0 592 601.483um^2 1434.960um^2 41.916% 0 0.000mw 0.000mw --- 0 0 0 5049 465 88 1003 354 5675 36229 10877.000um 5.280GB 43.549s 44.266s 02:06.546s
Toggle write_gds0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 0 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 583.008MB 04.610s 06.846s 02:13.926s
Toggle write_data0 Metrics
errors warnings drvs drcs unconstrained cellarea totalarea utilization logicdepth peakpower leakagepower irdrop holdpaths setuppaths macros cells registers buffers inverters pins nets vias wirelength memory exetime tasktime totaltime
0 40 19 --- 592 601.483um^2 1434.960um^2 41.916% 0 0.000mw 0.000mw 0.003mv 0 0 0 5049 465 88 1003 354 5675 --- --- 700.340MB 53.509s 54.704s 03:01.785s
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